1. Technical Field
The present invention is directed generally toward improved data storage. More particularly, the present invention relates to a method and apparatus in a data controller for retrieving, evaluating, and processing a context that describes a direct memory access request.
2. Description of the Related Art
One function of a data processing device is to move data based on a request, also referred to as a command, from an external system. For efficient operation, it is important that the data processing device maintains data movement between a requestor and a final storage medium without excessive processing overhead, whether the final storage medium is a disk drive, cd-rom drive, tape drive, flash memory or the like.
There are many approaches to controlling the movement of data based on a request from an external system. One approach is to use a microprocessor to process every boundary in the data flow via service interrupts. For example, when a request is made, an interrupt can be asserted to communicate to the microprocessor that a new command is available. The microprocessor can then evaluate the command and determine the size of the data transaction. If the request is a write command, the microprocessor allocates space to store the data, in either an internal or an external storage medium, and then processes the incoming data. A similar process is followed to read data from a storage medium in response to a read command.
The microprocessor may use a direct memory access (DMA) to physically move the write or read data between a requesting host device and the internal or an external storage medium associated with the storage device. Direct memory access uses specialized circuitry or a dedicated microprocessor to transfer data from memory to memory. For example, data may be moved from a buffer in a host bus adapter to a buffer in the storage device. The characteristics of a DMA transfer are typically defined using a context, which includes all of the information that is necessary in order for a storage controller included in the storage device to program a DMA transfer, whether that transfer is a read or a write. A context typically describes whether the transfer is to be a read or write to the drive, the length of the data to be transferred, and the current location of the data to be read or written.
The microprocessor may program a single context at a time, or it may queue up multiple contexts at a time for the DMA to transfer. A write DMA may exist for transferring the data represented by the queued write contexts and a read DMA may exist for transferring the data represented by the queued read contexts. For write contexts, the write DMA may be capable of swapping in the needed context as write data is received from the requesting host device. For read contexts, the read DMA usually continues to work on the same context until all the read data represented by the length of the context has been transferred to the requesting host device. When the DMA has completed the read context, then it can load another read context. As a result, when a read DMA is still working on the data transfer for a given read context, it is essentially blocked from transferring the data represented by other read contexts.
A storage area network (SAN) includes a SAN fabric, which is a combination of interconnected switches that collectively provide a routing infrastructure within the SAN. The SAN fabric may be, for example, a fibre channel (FC) fabric or other transport technology, such as a small computer system interface (SCSI) bus or, more particularly, serially attached SCSI (SAS) technology. In the SAS or FC bus protocol, full duplex transfers are possible. For example, as a initiator of commands in the system is sending new commands to a device, the device can simultaneously be returning read data from previous commands. This results in less time for the system to wait for this read data and improves system performance. In most of these protocols, the devices must arbitrate to gain access to transfer on the bus and there are cases when an arbitrating device might lose priority on the bus. For example, a device may configure a DMA read transfer for a pending command from a first initiator and then try to arbitrate for the SAS bus for this transfer. But then a second initiator may win arbitration on the SAS bus instead and open a connection to the device. The device may have other available read contexts whose data can be transferred on the open bus connection with the second initiator, but since the read DMA is already committed for a read context related to the first initiator, the device is not able to take advantage of the unexpected connection to the second initiator.
As another example, the read DMA may be transferring data for a read context when the host initiator device indicates that it wishes to close the bus connection without receiving the rest of the read data for this context. As in the lost arbitration case, the read DMA is again committed to the read context that it is currently working on and is unable to load another read context, perhaps for a different host initiator device, that would be more capable or higher priority for transferring data next in the read DMA. However, once the DMA is able to complete the transfer of the data represented by the programmed read context, then it can discard this context and choose a new context from the pool of queued read contexts. For example, now the DMA can choose the next context from the pool that is the highest priority for keeping the performance of the system high, where this priority may be a factor that is changing dynamically, for example, based on the amount of data that is ready to be transferred for a given context.
If an error or other exception condition occurs in any part of the handling of the request from a host initiator device, either the host initiator device or the data processing device may choose to abort the command or perform some other error handling procedure that may include altering or removing the context currently loaded in the read DMA. Since the read DMA is dynamic in nature, it can be simpler for the microprocessor to perform these procedures on contexts that are still in the pending pool of contexts instead of on the context that is loaded in the DMA.
From these examples, it is clear that a means is needed to put contexts that are loaded in a DMA back into the pending pool of contexts where it can be reconsidered in priority against the other pending contexts in the pool. These means must consider factors such as how the context has been modified since it has been in the DMA, the flushing of any pipeline that may exist between the pool and the DMA, and the communication with any logic associated with the pool that is tracking the state of the available contexts and deciding which context to send to the DMA next. The pipeline between the pool and the DMA may include local storage of one or more contexts that were chosen to be executed by the DMA after the context currently in the DMA assuming the DMA context completes normally. These contexts also need to be put back into the pool.